The Art of the Possible: Why PPA Deserves Better Than Guesswork

Semiconductor Manufacturing

Every chip designer knows the moment. The architecture is sketched, the RTL is written, and now comes the wait. Days turn into weeks as synthesis and place-and-route grind through the possibilities. By the time the PPA numbers arrive, the team has already moved on, or worse, committed to a path that might not have been the best one. It’s not a failure of talent. It’s a failure of timing. For decades, the industry has accepted this rhythm. But in Singapore, BoltChip, a small deep-tech team, is asking a different question: What if we could understand the PPA implications of our RTL before we commit to the full flow?

For decades, the industry has accepted this rhythm. But in Singapore, BoltChip, a small deep-tech team, is asking a different question: What if we could understand the PPA implications of our RTL before we commit to the full flow?

This isn’t about rushing. It’s about seeing clearly. PPA is not just three numbers; it’s a complex web of trade-offs. A decision that improves power might hurt performance. A smaller area might create routing congestion. These relationships are subtle, and they demand more than intuition. They demand data.

We’ve spent years studying those relationships. What we have built is a deep-tech machine learning model, trained on real post-route results, that predicts PPA straight from RTL. It is not an LLM guessing at code. It reads a design the way physical implementation will eventually see it: as structure, connectivity and constraints, not as lines of code. The model is accurate: 90%+ across 150+ open-source designs. And our next step is already underway, taking that same rigor into a leading commercial 28nm node, validated against real signoff results. Other nodes will follow. With this capability, a design engineer can explore a dozen micro-architecture options in a single morning, compare their trade-offs, and optimize the design before committing to the full flow. Prediction becomes the foundation for optimization: the engineer sees the path clearly, chooses the best one, and moves forward with confidence. Not to replace signoff, but to ensure that the option reaching signoff is the strongest one.

With this capability, a design engineer can explore a dozen micro-architecture options in a single morning, compare their trade-offs, and optimize the design before committing to the full flow. Prediction becomes the foundation for optimization: the engineer sees the path clearly, chooses the best one, and moves forward with confidence. Not to replace signoff, but to ensure that the option reaching signoff is the strongest one.

Today, our focus is Digital RTL. Next, we extend to Analog and mixed-signal, where PPA takes on a different meaning: precision, bandwidth, and power trade-offs that define analog excellence. Then to Packaging SI/PI. The ambition is a unified prediction capability across the entire design spectrum, from transistor to package. It’s a long road, but one worth walking. Singapore’s semiconductor ecosystem is world-class, built by pioneers and giants alike. We are humbled to add our own thread to that tapestry. Our models are tuned to your nodes and design history. Deployed on cloud or on-prem, so your data stays yours. Judged against your own signoff results.

Singapore’s semiconductor ecosystem is world-class, built by pioneers and giants alike. We are humbled to add our own thread to that tapestry. Our models are tuned to your nodes and design history. Deployed on cloud or on-prem, so your data stays yours. Judged against your own signoff results.

The road from RTL to signoff doesn’t have to be a black box. We believe it can be a conversation, one where data informs decisions, and exploration leads to confidence. If this vision resonates, we would welcome the chance to explore a pilot together, on one block of yours. Not to replace your flow, but to strengthen it. One step at a time, we can build what comes next.